Optimizing DSRC Systems through Combined Similarity-Oriented Logic Simplification and Manchester Encoding
DOI:
https://doi.org/10.46243/jst.2023.v8.i01.pp1-7Keywords:
Similarity-Oriented Logic Simplification, Differential Manchester Encoding, FM0 encoding, reduce functionalityAbstract
The significance of encoding strategies in communication systems cannot be overstated, with methods such as Manchester and FM0 encoding playing crucial roles in various applications. Each strategy exhibits distinct operations tailored to specific requirements. This paper introduces the Similarity-Oriented Logic Simplification technique (SOLS), which integrates design and synchronizes tasks, coupled with the use of Differential Manchester Encoding (DSRC) to maintain DC balance and signal reliability. The combination of these techniques aims to reduce the number of transistors and preserve DC balance. The current work focuses on achieving an integrated design of FM0 and Manchester encoding to address shortcomings in traditional methods. This approach results in a reduction in the number of hardware components, consequently minimizing the overall area occupied by additional functionality in Dedicated Short-Range Communication (DSRC) systems.
References
B. Melvin, “Let’s think analog,” in Proc. IEEE Com-put. Soc. Annu.Symp. VLSI, 2005, pp. 2–5
International Technology Roadmap for Semiconductors [Online].Available: http://public.itrs.net
B. Melvin and Z. Haiyang, “Error-tolerance and multimedia,”in Proc. 2006 Int. Conf. Intell. Inf. Hiding and Multimedia SignalProcess., 2006, pp. 521–524
M. A. Breuer, S. K. Gupta, and T. M. Mak, “Design and error tolerancein the presence of massive numbers of defects,” IEEE Des. TestComput., vol. 24, no. 3, pp. 216– 227, May-Jun. 2004
M. A. Breuer, “Intelligible test techniques to sup-port error-tolerance,”in Proc. Asian Test Symp., Nov. 2004, pp. 386–393
K. J. Lee, T. Y. Hsieh, and M. A. Breuer, “A novel testing methodologybased on error-rate to support errortolerance,” in Proc. Int. Test Conf.,2005, pp. 1136–1144
S. Chong and A. Ortega, “Hardware testing for error tolerant multimediacompression based on linear transforms,” in Proc. Defect andFault Tolerance in VLSI Syst. Symp., 2005, pp. 523– 531
H. Chung and A. Ortega, “Analysis and testing for error tolerant motionestimation,” in Proc. Defect and Fault Tolerance in VLSI Syst. Symp.,2005, pp. 514–522
H. H. Kuok, “Audio recording apparatus using an imperfect memorycircuit,” U.S. Patent 5 414 758, May 9, 1995
T. Y. Hsieh, K. J. Lee, and M. A. Breuer, “Reduction of detected acceptablefaults for yield improvement via errortolerance,” in Proc.Des., Automation and Test Eur. Conf. Exhib., 2007, pp. 1–6
V. Palem, “Energy aware computing through probabilisticswitching: A study of limits,” IEEE Trans. Comput., vol. 54, no. 9, pp.1123–1137, Sep. 2005
S. Cheemalavagu, P. Korkmaz, and K. V. Palem“Ultra low energycomputing via probabilistic algorithms and devices: CMOS deviceprimitives and the energy-probability relationship,” in Proc. 2004 Int.Conf. Solid State Devices and Materials, Tokyo, Japan, Sep. 2004, pp.402–403
P. Korkmaz, B. E. S. Akgul, K. V. Palem, and L. N. Chakrapani, “Advocatingnoise as an agent forultra-low energy computing: Probabilisticcomplementary metal-oxidesemiconductor devices and their characteristics,”Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3307–3316, 2006
E. Stine, C. R. Babb, and V. B. Dave, “Constant addition utilizingflagged prefix structures,” in Proc.IEEE Int. Symp. Circuits and Systems(ISCAS), 2005
L.-D. Van and C.-C. Yang, “Generalized low-error areaefficient fixedwidthmultipliers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 25,no. 8, pp. 1608–1619, Aug. 2005
Lehman and N. Burla, “Skip techniques for high-speed carry propagationin binary arithmetic units,” IRE Trans. Electron. Comput., vol.EC-10, pp. 691–698, Dec. 1962
O. Bedrij, “Carry select adder,” IRE Trans. Electron. Comput., vol.EC-11, pp. 340–346, 1962
O. MacSorley, “High speed arithmetic in binary computers,” IRE Proc.,vol. 49, pp. 67–91, 1961
Y. KiatSeng and R. Kaushik, Low-Voltage, Low-Power VLSI Subsystems. New York: McGraw-Hill, 2005
